1. The Field of the Invention
The present invention generally relates to printed circuit boards (PCBs). More particularly, the present invention relates to systems and methods for fabricating printed circuit boards and more specifically to systems and methods for plating traces on PCBs.
2. The Relevant Technology
An integral component of many electrical and optical devices is a multi-layer printed circuit board (PCB). PCBs are used, for example, to route signals and provide connections to various electrical and/or optical components. During plating, which is one of the steps that occurs during the fabrication of a PCB for example, some or all of the traces, vias, pads, etc., are plated with hard gold. Plating ensures that the PCB can make a solid electrical connection and strengthens the electrical integrity of the PCB. Usually, all features of the PCB requiring plating are plated at the same time.
The typical plating process involves shorting all the contact pads by connecting them to small traces, which extend off the front edge of the PCB. The small traces then connect to a plating bar and a voltage is applied. By connecting all of the traces to a plating bar, all of the signal paths requiring plating in the PCB form a single conductive path. By applying a voltage, the resulting current electronically plates the gold on to the contact pads. In other words, all necessary signal paths are plated with hard gold at the same time. After the plating process is complete, the traces used to plate the appropriate portions of the PCB are cut at the front edge of the PCB, thus eliminating the short between the contact pads. One of the problems with this process is that small traces that extend from the contact pads to the front edge of the PCB remain on the PCB.
This problem is illustrated in FIG. 1 where the traces used to plate the contact pads (and other traces, signals, vias, etc. of the PCB) remain after the PCB has been routed to a final form factor. In FIG. 1, the contact pads 102 provide electrical access to the signal or conductive paths of the PCB 100. As previously described during the plating process, the traces 104 were formed and connected to a plating bar (not shown). Thus, the PCB 100 illustrates the traces 104 that were used to plate the contact pads 102 and other conductive paths of the PCB 100. Note that FIG. 1 illustrates the contact pads of the PCB 100, but it is understood that the other conductive paths that are connected with the contact pads are also plated.
Unfortunately, the traces 104 are in the area 106 between a front edge 103 of the PCB and the contact pads 102. The presence of the small traces 104 in the area 106 of the PCB 100 may violate certain standards. In particular, the traces 104 may violate the GBIC/MSA standard. This standard requires that the contact pads within a GBIC/MSA device be set back from the PCB edge. Other small form factor pluggable standards (GBIC, SFP, XFP) may have similar requirements.
Another problem produced by the typical plating process is that it may interfere with high-speed traces, which are connected to certain contact pads. The purpose of the high-speed traces is to send high-speed data through the PCB. To achieve this purpose, high-speed traces involve careful balancing of impedances. The small traces that extend from the contact pads to the edge of the PCB disrupt this balance and reduce the ability of the high speed traces to effectively transfer data at high speeds. Cutting the small traces produces large stubs at the edge of the PCB, which do not affect performance of low speed traces but create interference among the high-speed traces and adversely affect the performance of these high-speed lines.
Previous attempts to improve the plating process and eliminate the extension of small traces to the front edge of the PCB have been unsatisfactory. For example, etching, a technique employed to remove the small traces 104 from the area 106 of the PCB after the plating process, is expensive for use in low-cost transceiver modules.